FSM Decomposition for Low Power in FPGA

In this paper, the realization of low power finite state machines (FSMs) on FPGAs using decomposition techniques is addressed. The original FSM is divided into two submachines using a probabilistic criterion. Only one submachine is active at a time, meanwhile the other is disabled to save power. Different deactivation alternatives and state encoding have been studied. For each option, actual measurements of power consumption have been done using the MCNC and the PREP benchmark circuits. A Xilinx XC4K device has been utilized as technological framework. The proposed technique fits well with big FSM, where power reductions up to 46% are obtained.